1. Field of the Invention
The present invention relates to a method of fabricating fringe field switching mode liquid crystal display (hereinafter referred to as FFS-LCD), and more particularly to a fabrication method of FFS-LCD capable of preventing shorts between a gate bus line and a common electrode line.
It is well known that a FFS-LCD has been proposed in order to improve a low aperture ratio and a transmittance of IPS (In Plane Field Switching)-LCD.
In the FFS-LCD, a counter electrode and a pixel electrode are made of transparent conductors and the distance between the electrodes is narrower than that of an upper and a lower substrates to form a fringe field on the electrodes and thereby, drive all of liquid crystal molecules thereon.
A conventional method of fabricating FFS-LCD will be described in conjunction with FIGS. 1 and 2.
FIG. 1 is a cross-sectional view for showing a conventional method of fabricating FFS-LCD and FIG. 2 is a layout thereof.
Referring to FIG. 1, an ITO layer is first deposited on a lower substrate 11 and then selectively patterned to form a counter electrode 12.
Subsequently, a metal layer (not shown) is deposited on the lower substrate 11 having the counter electrode 12 thereon, to a predetermined thickness and then selectively patterned to form a gate bus line 13, a gate electrode 13a extended from the gate bus line 13 and a common electrode line 130.
Here, the common electrode line 130 is in contact with a predetermined part of the counter electrode 12, being in parallel with the gate bus line 13.
After formation of the gate bus line 13 and the common electrode line 130, a gate insulating layer 14, an amorphous silicon layer for channel and a doped semiconductor layer are sequentially deposited on the lower substrate 11.
The amorphous silicon layer for channel and the doped semiconductor layer are then selectively patterned in order to form a thin film transistor region, thereby forming a channel layer 15 and an ohmic layer 16.
And then, a metal layer (not shown) is deposited on the surface of resulting structure and selectively patterned to overlap with both sides of the channel layer 15 and a part of the gate bus line 13, thereby forming a source 17a, a drain 17b and a data bus line 17.
Thereafter, a protective layer 18 is deposited on the resulting lower substrate 11 and selectively etched to expose the drain 17b. Then, a pixel electrode 19 is formed on the protective layer 18 in a slant shape, being in contact with the exposed drain 17b. 
In this FFS-LCD, a fringe field is formed between a slant part of the pixel electrode 19 and counter electrode 12 exposed by the slant part, thereby driving all of the liquid crystal molecules on the pixel electrode 19 and the counter electrode 12.
However, a conventional FFS-LCD has several problems since a gate bus line 13, a common electrode line 120 and a counter electrode 12 are formed on the same plane.
However, a conventional FFS-LCD has several problems since a gate bus line 12, a common electrode line 120 and a counter electrode 13 are formed on the same plane.
Therefore, a method has been proposed in that the counter electrode 12 is formed by depositing an ITO layer on the lower substrate 11 and then a metal layer is deposited thereon and selectively patterned to form the gate bus line 13 and the common electrode line 130.
However, the ITO layer is generally etched by a wet-etching process and the etching property is very poor. Therefore, the ITO layer remains to some extent after etching process for forming the counter electrode 12.
This residues of ITO layer 120 may be formed wherever on the lower substrate 11 and operates as a bridge between the gate bus line 13 and the common electrode line 130.
As a result, shorts are generated between the gate bus line 13 and the common electrode line 130 by the residues of ITO layer 120, thereby decreasing yield of FFS-LCD.
Therefore, the present invention has been made to solve the above problems. The object of the present invention is to provide a method of fabricating FFS-LCD capable of preventing shorts between a gate bus line and a common electrode line.
In order to achieve the above object, the present invention comprises the steps of: forming a gate bus line and a common electrode line on a lower substrate in parallel with each other; forming a gate insulating layer on the lower substrate; forming a counter electrode on the gate insulating layer to overlap with a predetermined part of the common electrode line; depositing a metal layer on the resulting lower substrate and then selectively patterning the layer, thereby forming a contacting part connecting the counter electrode and the exposed common electrode line; depositing a protective layer on the lower substrate obtained after formation of the source/drain and the contacting part; selectively etching the protective layer to expose a predetermined part of the drain; and forming a pixel electrode on the protective layer to form a field with the counter electrode, being in contact with the drain.